This invention generally relates to a semiconductor integrated circuit. More particularly, this invention relates to a circuit having complementary metal oxide semiconductor type inverters.
Metal oxide semiconductor (MOS) type field effect transistors (FETs) are widely used in integrated circuits (ICs), especially complementary MOS (CMOS) FETs which are used for inverters having various circuits, such as a peripheral circuit of a dynamic random access memory (DRAM) device.
FIG. 1(a) shows a circuit diagram of a double stage inverter circuit. The first stage is composed of a p channel FET Tp1, and an n channel FET Tn1. The FETs are connected in series between a positive voltage source line Vcc1 and a negative voltage source line Vss1. The gate electrodes of these transistors are connected to each other, and G1 a first junction point of these gates is connected to an input terminal Din. The source electrodes Sp and Sn of these transistors are respectively connected to the Vcc1 or Vss1, while the drain electrodes Dp and Dn of these FETs are connected to each other, and outputs an inverted signal to a first output signal line N1 which feeds the inverted signal to the second stage inverter. The second stage inverter is also composed of a p channel FET Tp2 and an n channel FET Tn2. These transistors are connected similarly to the first inverter. These transistors receive the inverted signal from the first signal line N1 at a second junction point G2, and output the signal to a second output signal line N2 which is connected to an output terminal Dout. The second voltage source line Vss1 is usually grounded.
FIG. 1(b) is a schematic plan view illustrating an exemplary arrangement of elemental devices on an IC chip showing a portion of a double stage inverter circuit, as shown in FIG. 1(a). The p-channel FETs Tp1, Tp2 and the n-channel FETs Tn1, Tn2 are formed in a semiconductor substrate. These FETs are separated from each other by a field oxide layer and coated by a gate oxide layer. The insulation layers are not shown in FIG. 1(b), but they can be considered to be coating for the entire surface of the substrate. The gate electrodes G1 and G2 are usually formed with a doped polysilicon layer deposited on the gate oxide layer. The entire surface of the substrate is further coated with an insulation layer, such as, silicon dioxide (SiO.sub.2) which will be called first insulation layer hereinafter. The first insulation layer is also not shown in FIG. 1(b) because it is coating for the entire surface of the substrate. The voltage source lines Vcc1, Vss1 and the signal lines N0, N1, N2 are formed over the first insulation layer by patterning an aluminum film, for example. They are respectively identified in FIG. 1(b) with a double dot chain line, a single dot chain line and broken lines. These wiring patterns are connected to corresponding electrodes Sp, Sn, Dp, Dn, G1, G2 through respective contact holes formed through the insulation layers. These contact holes are identified by cross hatched areas in FIG. 1(b).
The configurations inverter circuits cause several problems when packing density of the elemental devices in the IC becomes high. Generally, the voltage source lines Vcc1 and Vss1 are required to be wider compared to other wiring lines, such as, G1, G2 or N0, N1, N2 because voltage source lines have to carry a larger current than those of other wiring lines. If the aluminum wiring lines are made too narrow, the current density in the wiring line increases which causes electro-migration of aluminum, and the reliability of the device decreases; thereby, reducing the size of the device. Further, as can be seen in FIG. 1(b), the voltage source lines Vcc1, Vss1 and the signal lines N0, N1, N2 are formed on a same layer (the first insulation layer) with the same aluminum film. Accordingly, the Vcc1 or Vss1 lines must be arranged in an outside area of the device, and extended branch members B toward the inside of the device in order to contact with respective electrodes Sp or Sn since the voltage source lines Vcc1, Vss1 have to be separated from the signal lines N0, N1, N2 which are arranged at the center part of the device. Accordingly, a limitation on the design to reduce the size of the device size is set.